With the increasing demand for pursuing higher performance in semiconductor industries, the package technology has been evolved from two-dimension (2D) to three-dimension (3D) wafer package, so as to further improve the density and performance of circuits in an integrated circuit devices.
In the 3D wafer package, two wafers are bonded with conductive pads, and through silicon via (TSV) electrodes are then formed to interconnect conductive pads on the first and second wafers. The TSV electrode is usually made of copper or other conductive material to provide electrical connections between conductive pads. However, due to a large mismatch of coefficients of thermal expansion (CTEs) between copper, or other conductive material of the TSV electrode, and silicon of a substrate surrounding the TSV electrode, structural instability and some defects may occur owing to a thermal stress induced by the large mismatch of CTEs. Thus, further improvements are needed to solve the aforementioned problems and enhance performance of semiconductor device.